A Unified Tile-Level Execution and Tracing Framework for GPU Kernel Simulation

Abstract

Tile-based programming models such as Triton and NVIDIA's cuTile are now standard tools for writing high-performance GPU kernels. Because each defines its own intermediate representation and execution abstraction, there is no common way to reason about kernel behavior across them, and existing compiler toolchains rarely expose execution traces detailed enough for performance modeling. This work develops a unified tile-level execution and tracing framework as the frontend of a trace-driven GPU performance simulator. A common Tile Execution IR captures a kernel's functional behavior: tile loads and stores, matrix multiplication, element-wise arithmetic, reductions, loops, and boundary masks, with the memory region each operation touches and the dependencies among them. An abstract interpreter executes a kernel in this IR and, in the same pass, emits a compact semantic trace. Frontend adapters lower kernels from Triton-like and cuTile-like source and from NVIDIA CUDA Tile IR into the shared representation. The prototype runs representative kernels, including vector addition, matrix multiplication, transpose, and reductions. Each is checked against an independent reference for numerical equivalence and dependency structure, with operation counts and memory traffic read from the trace. Matrix-multiplication kernels lowered from CUDA Tile IR reproduce the reference bit-for-bit, and every executed operation appears exactly once in the trace. The trace records what a kernel computes, not how a particular device times it. Planned extensions add warp- and warpgroup-level mappings, asynchronous data movement, pipeline stages, synchronization, and architecture-specific latency models. By separating logical behavior from any one hardware model, the framework gives tile-level trace-driven simulation and design-space exploration a language-independent foundation.